Logic built in self test circuitry for use in an integrated circuit with scan chains

ABSTRACT

Aspects include a method for logic built-in self-testing (LBIST) for use in an integrated circuit with scan chains. The method includes programming a product control generator and a pattern generator with an LBIST pattern comprising at least a number of loops. The LBIST pattern is executed by generating scan-in test values for scan chains with the pattern generator and controlling at least one test parameter with the product control generator. Scan-out responses are collected from the scan chains in a signature register, and a start request is received from a chip tester. The LBIST is started in response to the start request. Test summary data is reported to the chip tester before the whole number of loops has been executed.

BACKGROUND

The present invention generally relates to testing integrated circuitsand, more specifically, to logic built-in self-test (LBIST) circuitryfor use in an integrated circuit with scan chains.

Digital integrated circuits are used for a diverse number of electronicapplications, from simple devices such as wristwatches to the mostcomplex computer systems. Defects in digital integrated circuits mayoccur.

“Stored patterns” was one of the first methods developed for testingdigital integrated devices for defects. According to the stored patternsmethod, a value per latch of the device under test (DUT) is defined, andthis data is stored in a chip tester and applied upon pattern execution.Similarly, a clock or capture sequence may be stored. After thefunctional clock sequence execution, the chip tester receives themeasured values per latch and compares them with the expected values todetermine defects in the DUT. The stored patterns method requires accessof the chip tester to each latch to be tested of the DUT. With millionsof latches on a chip this becomes a very time-consuming operation.

LBIST has become a popular technique for on-chip testing of digitalintegrated circuits. LBIST offers a number of benefits targeted at thereduction of test time.

The scannable latches of the DUT may be broken into short scan chainsand the major components of LBIST circuitry include a pattern generator,a signature register and an on-product test control generator.

The pattern generator is initialized with a seed and provides scan-invalues to the scan chains. A clocking sequence is applied on the DUT andthe signature register collects scan-out responses from the scan chains.

The chip tester only needs to store an LBIST setup that includes theseed, the loop count, and the clock sequence. As the scan-in values aregenerated on the DUT at higher speeds compared to the testercommunication speed, the time necessary per loop is significantlyreduced.

As technology advances, the number of transistors on a chip increasesand the number of defects during manufacturing may increase, inparticular when a new manufacturing process is introduced. Moreover,said defects may be difficult to detect. Accordingly, more thoroughtesting may be required, which consumes more time and augments the testtime.

SUMMARY

Embodiments include a method, system, and computer program product forlogic built-in self-testing (LBIST). A method includes programming aproduct control generator and a pattern generator with an LBIST patterncomprising at least a number of loops. The LBIST pattern is executed bygenerating scan-in test values for scan chains with the patterngenerator and controlling at least one test parameter with the productcontrol generator. Scan-out responses are collected from the scan chainsin a signature register, and a start request is received from a chiptester. The LBIST is started in response to the start request. Testsummary data is reported to the chip tester before the whole number ofloops has been executed.

Additional features and advantages are realized through the techniquesof the present invention. Other embodiments and aspects of the inventionare described in detail herein and are considered a part of the claimedinvention. For a better understanding of the invention with theadvantages and the features, refer to the description and to thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The forgoing and other features, and advantages ofthe invention are apparent from the following detailed description takenin conjunction with the accompanying drawings in which:

FIG. 1 shows an integrated circuit that includes logic built-inself-test (LBIST) circuitry in accordance with some embodiments of thisdisclosure;

FIG. 2 is a flow chart illustrating a LBIST method in accordance withsome embodiments of this disclosure;

FIG. 3 is a flow chart illustrating another LBIST method in accordancewith some embodiments of this disclosure;

FIG. 4 shows a further integrated circuit comprising LBIST circuitry anda chip tester in accordance with some embodiments of this disclosure;

FIG. 5 is a flow chart illustrating an additional LBIST method inaccordance with some embodiments of this disclosure;

FIG. 6 is a flow chart illustrating a LBIST method with communicationwith a tester (ATE) in accordance with some embodiments of thisdisclosure;

FIG. 7 illustrates another LBIST method with communication with ATE inaccordance with some embodiments of this disclosure; and

FIG. 8 shows a still further LBIST method with communication with ATE inaccordance with some embodiments of this disclosure.

DETAILED DESCRIPTION

Embodiments of the present invention may be better understood, and itsnumerous objects, features, and advantages made apparent to thoseskilled in the art by referencing the accompanying drawings.

The embodiment shown in FIG. 1 discloses an integrated circuit 101comprising logic built-in self-test (LBIST) circuitry 102 and scanchains 103. The LBIST circuitry 102 includes a pattern generator 104, asignature register 105 and an on-product control generation 106.

The pattern generator 104 is adapted to generate scan-in values for thescan chains 103 and the multi input register 105 to collect scan-outresponses from the scan chains 103. The on-product control generation106 provides the necessary control for steering the pattern generator104, the scan chains 103 and the signature register 105 as well asdriving the clock sequence to the functional logic.

Moreover, the LBIST circuitry comprises a microcode array 107 withinputs to initialize its fields. Test control means 108 (or testcontroller) comprise reading means (or reader) (not shown) to read testparameters from a field of the microcode array 107. Furthermore, thetest control means 108 include programming means (not shown) responsiveto the reading means to configure the pattern generator 104 and theproduct control generation 106 with the read test parameters.

The test parameters may include a type of clock sequence, a number ofloops, a scan clock rate and a weight.

Typically, the probability that a binary scan-in value generated by thepattern generator is “0” will be 1/2. Applying a weight to the patterngenerator may change the probability to 1/8, 7/8, 1/16, 15/16, 1/32,31/32, 1/64 or 63/64, respectively. This may enhance the chance todetect a particular defect in the DUT an AND or OR gate having a largenumber of inputs.

Clocking sequence may include a launch-off clock and/or a launch-offscan. A launch-off clock may be used primarily to detect DC defects. Alaunch-off scan may be used primarily to detect AC defects. Furthermore,defects may only show up at a specific scan clock rate or with aspecific clock sequence.

Performing several loops with the same weight, the same type of clocksequence and the same clock rate may increase test coverage at limitedincreased test time as the setup is only necessary once.

A set of test parameters to be applied to the DUT, i.e. the patterngenerator 104 and the on-product control generation 106, may also becalled an LBIST pattern.

From the fields of the microcode array 107 several different LBISTpatterns may be derived. The test control means (or test controller) mayapply these LBIST patterns on the DUT in the stored sequence or in arandom order.

Each design of an integrated circuit may have its particular design fortest (DFT) requirements. The disclosed LBIST circuitry may supportexecuting LBIST patterns with different variations in view of theparticular DFT requirements.

The described LBIST circuitry has to be initialized only once by thechip tester before performing the LBIST. In particular, only the fieldsof the microcode array 107 have to be initialized. Thereafter, thedifferent LBIST patterns may be executed automatically. Hence,considerable chip tester time may be saved compared to conventionalLBIST circuitry, where every LBIST pattern has to be initializedseparately by the chip tester.

For example, if DFT requires three different clock sequences and fourdifferent weights to achieve the target test coverage. The test controlmeans 108 of the LBIST circuitry would sequence through and execute alltwelve combinations and weights with only one initialization of theLBIST circuitry by initializing the fields of the microcode array.Moreover, only one value from the signature register may be required todetermine, whether the LBIST circuitry passed the test trough all saidtwelve LBIST patterns or if it failed.

A LBIST method like that shown in the embodiment of FIG. 2 may bedescribed with reference to FIG. 1. In a first step 201, the chip testerinitializes the LBIST circuitry with a setup for a number of LBISTpatterns. A first LBIST pattern is executed according to the second step202. After the execution step 202 it is determined, whether all LBISTpatterns have been executed (step 203). If not, the next LBIST patternis executed pursuant to step 202. After all LBIST patterns have beenexecuted the final values in the signature register are transmitted tothe chip tester for evaluation (step 204).

FIG. 3 shows another embodiment of a LBIST method. First, the chiptester initializes the fields of the microcode array and transmits astarting signal to the LBIST circuitry (301). Thereafter, an LBISTpattern is read from fields of the micro array (302) and the on-productcontrol generation and a pattern generator is programmed according tothe LBIST pattern (303). After running the LBIST pattern (304),collected scan-out responses from scan chains of the integrated circuitare compared with the expected data (305). If there is no agreement, theLBIST circuitry reports an error to the chip tester (306) and the LBISTis stopped (308). In case no error is detected, it is determined whetherthe executed LBIST pattern has been the last one (307). If true, theLBIST is stopped (308). If false, the next LBIST pattern is read fromfields of the micro array (302).

FIG. 4 shows another embodiment of an integrated circuit 401 with scanchains 403 and LBIST circuitry 402. The LBIST circuitry 402 comprises apattern generator 404, a signature register 405 and an on-productcontrol generation 406.

The pattern generator 404 may be configured for generating scan-invalues for the scan chains 403. The signature register 405 receives thescan-out responses from the scan chains 403. The product controlgeneration 406 controls the steering for driving the pattern generator404, the scan chains 403, and the signature register 405 as well asdriving the clock sequence to the functional logic to be tested.

Furthermore, the LBIST circuitry comprises a microcode array 407including inputs for initializing the fields of the microcode array 407.Additionally, test control means 408 with reading means (not shown) andprogramming means (or programming component) (not shown) are provided.The reading means are adapted to read test parameters from fields of themicrocode array 407 and the programming means are configured to programthe pattern generator 404 and the product control generation 406 withthe read test parameters. The test control means also include an LBISTmeasure register 409 for temporarily storing the LBIST measure values ofthe signature register 405 and a flag indicating that an LBIST patternhas been completely executed.

Moreover, a chip tester 410 is depicted in FIG. 4 in schematic form. Thechip tester 410 comprises a chip tester logic 411 and an expected testresult memory 412. The chip tester logic 411 may be adapted to start theLBIST of the integrated circuit 401, i.e. the device under test (DUT).The chip tester logic may determine whether a flag in the LBIST measureregister 409 has been set indicating that an LBIST pattern has beencompletely executed has been set and, depending on the result, todownload or read the LBIST measure values from the LBIST measureregister. The downloaded or read LBIST measure values may then becompared with the expected LBIST values for the specific LBIST pattern,which are stored in the expected test result memory 412.

A still further embodiment of a LBIST method may be explained withreference to FIG. 5. As has been described hereinbefore, the methodstarts with initializing the fields of a microcode array of the LBISTcircuitry (501). Thereafter, a first LBIST pattern is executed (502),the LBIST measure values obtained by the signature register aretransmitted into an LBIST measure register of the test control means,and sets a flag in the LBIST measure register indicating that the LBISTpattern has been executed (503). Additionally, information indicative ofthe applied LBIST pattern (number of clocks, type of clock sequence,weight) may be stored in the LBIST measure register to allow directmatching between these parameters and the signature by the tester. Thisallows to swap the sequence of tests without needed new tester comparesequence. Swapping the sequence of tests is useful to have the test withthe highest fall out statistical rate first to reduce test time. If itis determined in step 504 that the executed LBIST pattern was the lastone, the LBIST is stopped (505). Otherwise, the steps 502 to 504 arerepeated.

The interaction of a chip tester 602 and a DUT 601, the microcode ofwhich has been initialized before, may be explained with reference tothe embodiment shown in FIG. 6. After starting of the LBIST in step 603,the DUT executes an LBIST pattern (604), reads the LBIST measure valuesfrom the signature register (605) and submits a test summary to the chiptester via output pins (606). Upon completion of the submission, the DUTsends a completion signal to the chip tester (607). These steps arerepeated until it is determined that the last LBIST pattern has beenapplied in step 608 and the LBIST is stopped (614).

The chip tester repeatedly determines whether a completion signal hasbeen received (609). Upon reception of such a signal, the test summaryis evaluated (610). If it is detected that the test summary is valid(611), i.e. the test summary corresponds to the expected result, it isdetermined whether it has been the last LBIST pattern (612). If this isthe case, the chip tester stops testing (614). Otherwise, steps 609 to612 are repeated.

If the test summary does not correspond to the expected result in step611, the chip tester outputs and error signal or flag (613) and stopstesting as well (614).

FIG. 7 shows another embodiment of a LBIST method. As has been explainedhereinbefore, the microcode array is initialized and the LBIST isstarted in a first step 701. Thereafter, in step 702, a first LBISTpattern is executed. A test summary derived from the scan-out valuescollected by the signature register is provided for a chip tester, whichmay also be called automatic test equipment (ATE), in step 703. In step704, the LBIST circuitry waits for the ATE to submit a continue signal.Upon receipt of the continue signal the LBIST circuitry determines instep 705, whether all LBIST patterns have been executed. If not, thepreceding steps 702 to 705 repeated. Otherwise, the LBIST is stopped(706).

FIG. 8 illustrates a still further embodiment of a LBIST method. TheLBIST method starts with initializing the microcode and starting theLBIST in step 801. Afterwards, a first LBIST pattern is executed (step802) and the test summary derived from the scan-out values collected bythe signature register is provided for the ATE (step 803). In Step 804it is determined if this was the last pattern. If not, the steps 801 to804 are repeated. In case the ATE determines that the provided signatureis incorrect or all LBIST patterns have been executed, the ATE may stopthe LBIST.

According to a first aspect, an embodiment of the invention relates toLBIST circuitry for use in an integrated circuit with scan chains,comprising (but not limited to) a pattern generator for generatingscan-in test values for said scan chains; a signature register forcollecting scan-out responses from said scan chains after a clocksequence; an on-product control generation to control at least one testparameter; test control means comprising: programming means to configuresaid on-product control generation and said pattern generation with anLBIST pattern comprising at least a number of loops; communication meansto communicate with a chip tester, comprising: receiving means (orreceiving component) to receive a start request from said chip tester;starting means (or starting component) responsive to said receivingmeans to trigger said test control means; reporting means (or reportingcomponent) responsive to said test control means to communicate testsummary data to said chip tester before the whole number of loops hasbeen executed.

According to a second aspect, an embodiment of the invention relates toa LBIST method comprising: programming a product control generation anda pattern generator with an LBIST pattern comprising at least a numberof loops; executing the LBIST pattern by generating scan-in test valuesfor scan chains with the pattern generator and controlling at least onetest parameter with the product control generation; collecting scan-outresponses from the scan chains in a signature register; receiving astart request from a chip tester; starting the LBIST in response to thestart request; reporting a test summary data to the chip tester beforethe whole number of loops has been executed.

Communicating test summary data to the chip tester before the wholenumber of loops has been executed may allow for a time-savinginterruption of the LBIST in case a defect is detected. For a giventotal tester time available, this may allow for a more thorough testingof goods DUTs by faster sorting out defective DUTs.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiments were chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

The present invention may be a system, a method, and/or a computerprogram product. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent invention.

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present invention may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Java, Smalltalk, C++ or the like,and conventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer may be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection may be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof instructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

1. A system comprising logic built-in self-test (LBIST) circuitry foruse in an integrated circuit with scan chains, the system comprising: apattern generator configured for generating scan-in test values for saidscan chains; a signature register configured for collecting scan-outresponses from said scan chains after a clock sequence; an on productcontrol generator configured to control at least one test parameter; anda test controller comprising: a programming component configured forconfiguring the on product control generator and the pattern generatorwith a LBIST pattern comprising at least a number of loops; and acommunication component configured for communicating with a chip tester,the communication component comprising: a receiving component configuredfor receiving a start request from the chip tester; a starting componentconfigured for triggering the test controller responsive to saidreceiving component; and a reporting component configured for,responsive to said test controller, communicating test summary data tosaid chip tester before the whole number of loops have been executed. 2.The system of claim 1, wherein the reporting component is furtherconfigured for communicating test summary data to said chip tester uponcompletion of the whole number of loops.
 3. The system of claim 1,further comprising: a microcode array or memory elements configured toreceiving inputs to initialize fields in the microcode array or memoryelements; wherein the test controller further comprises: a readercomponent configured for reading test parameters from a field of themicrocode array or the memory elements, wherein the test parametersinclude one or more of number of loops, clock sequence, weight, seed,read/write the on-chip array, variables for the scan itself andmasks/aperture, wherein the programming component is further configuredfor, responsive to the reading component, configuring the on-productcontrol generator and the pattern generator with an LBIST patternaccording to the read test parameters.
 4. The system of claim 3, whereinthe test controller is configured to repeatedly read test parametersfrom a field of said microcode array or the memory elements via thereader component and to configure the on-product control generator andthe pattern generator with the LBIST patterns according to the read testparameters sequentially.
 5. The system of claim 3, wherein the testcontroller is configured to repeatedly read test parameters from a fieldof said microcode array or the memory elements via the reader componentand to configure the on-product control generator and the patterngenerator with the LBIST patterns according to the read test parametersrandomly.
 6. The system of claim 1, wherein the test summary datacomprises information indicative of the applied LBIST pattern. 7.(canceled)
 8. (canceled)
 9. (canceled)
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 11. (canceled) 12.(canceled)
 13. (canceled)
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 18. A computer program product for logic built-inself-testing (LBIST), the computer program product comprising a computerreadable storage medium having program instructions embodied therewith,the program instructions executable by a processor to cause theprocessor to perform: programming a product control generator and apattern generator with an LBIST pattern comprising at least a number ofloops; executing the LBIST pattern by generating scan-in test values forscan chains with the pattern generator and controlling at least one testparameter with the product control generator; collecting scan-outresponses from the scan chains in a signature register; receiving astart request from a chip tester; starting the LBIST in response to thestart request; reporting a test summary data to the chip tester beforethe whole number of loops has been executed.
 19. The computer programproduct of claim 18, wherein the program instructions further cause theprocessor to perform: initializing fields of a microcode array or memoryelements; reading test parameters from a field of the microcode array ormemory elements, wherein the test parameters include one or more ofnumber of loops, clock sequence, weight, seed, read/write the on-chiparray, variables for the scan itself and masks/aperture; and programmingthe product control generation and the pattern generator with the LBISTpattern according to the read test parameters.
 20. The computer programproduct of claim 18, wherein the program instructions further cause theprocessor to perform: repeatedly reading the test parameters andprogramming the product control generation and the generator with theLBIST patterns in sequential order.